a. Field of the Invention
The present invention relates to the programming and erasing of nonvolatile memory devices. More particularly, the present invention relates to a scheme for flash cell recovery from a Fowler-Nordheim tunneling program and/or erase process.
b. Description of Related Art
Flash memory is a class of nonvolatile memory integrated circuits, based on floating gate transistors. The memory state of a floating gate cell is determined by the concentration of charge trapped in the floating gate. The operation of flash memory is largely dependent on the techniques used for injected or removing charge from the floating gate.
There are at least two basic techniques utilized for moving charge into and out of floating gate memory cells. A first technique is referred to as hot electron injection. Hot electron injection is induced by applying a positive voltage between the drain and source of the memory cell, and a positive voltage to the control gate. This induces a current in the cell, and hot electrons in the current are injected through the tunnel oxide of the floating gate cell into the floating gate. Hot electron injection is a relatively high current operation, and is therefore usually limited to use for programming a few cells at a time in the device.
A second major technique for moving charge into and out of the floating gate of flash memory cells is referred to as Fowler-Nordheim tunneling (F-N tunneling). F-N tunneling is induced by establishing a large electric field between the control gate and one of the drain, source, and channel or between the control gate and a combination of these terminals. The electric field establishes a F-N tunneling current through the tunnel oxide and can be used for both injecting electrons into the floating gate, and driving electrons out of the floating gate. The F-N tunneling process is relatively low-current, because it does not involve a current flowing between the source and drain of the cells. Thus, it is commonly used in parallel across a number of cells at a time on a device.
Operation of flash memory involves programming the array, which requires a cell-by-cell control of the amount of charge stored in the floating gate, and erasing by which an entire array or a sector of the array is cleared to a predetermined charge state in the floating gate. In one kind of flash memory, F-N tunneling is used both for programming and for erasing cells in the array.
The F-N tunneling erase used in prior approaches, has been a limiting factor on the ability to use low supply voltages (VDD less than 5 volts) with the integrated circuit chips. For example, one common approach is based on a memory cell formed in a p-type semiconductor substrate having n-type source and drain regions. A source-side F-N tunneling erase operation is biased by applying an erasing potential of about twelve volts to the source, grounding the substrate, and setting the word line connected to the control gate of the cells to be erased at zero volts. Thus, an erase operation is achieved by F-N tunneling between the source and the floating gate. However, a large voltage difference (12 volts) is established between the source and the substrate. This voltage difference induces unwanted substrate current and hot hole current. To suppress the unwanted current a so-called double diffusion source process is used. The double diffusion creates a gradual or two stage change in concentration of n-type doping between the source and the substrate. This reduces the stress at the interface between the source and the substrate, and suppresses the unwanted current. However, the double diffusion source limits the ability to shrink the size of the cell.
An alternative approach involves the use of a triple well floating gate memory such as that disclosed in International Patent Application No. PCT/US97/03861, entitled "Triple Well Floating Gate Memory and Operating Method with Isolated Channel Program, Preprogram and Erase Processes", invented by Ray-Lin Wan and Chun-Hsiung Hung, and assigned to the assignee of the present invention. In one embodiment of this approach, the flash cell is formed in a p-type substrate, in which a deep n-well (NWD) is formed within a p-well inside (PWI). N-type source and drain regions are formed within the PWI. A typical manner of F-N programming of this triple well floating gate arrangement is illustrated with respect to FIG. 1, in which it is shown that the p-substrate is connected to ground, the NWD to a small positive voltage of approximately 3 volts, the PWI, source, and drain are connected to a negative voltage of approximately -9 volts, and the gate is connected to a positive voltage of approximately 8 volts. A typical manner of F-N erasing of this triple well floating gate arrangement is illustrated with respect to FIG. 2, in which it is shown that the p-substrate is connected to ground, the NWD to a large positive voltage of approximately 10 volts, the PWI, source, and drain are connected to a positive voltage of approximately 6 volts, and the gate is connected to a negative voltage of approximately -9 volts. After performing a program or erase of the cell, the potentials applied to the nodes must be moved away and recovered to ground potential, this is known as the recovery of the cell.
In designing a scheme to program and erase a triple well floating gate cell as illustrated in FIGS. 1 and 2, one major factor to be considered is the speed at which the program/erase functions can be performed. The speed at which the cell can recover from the high voltages applied to the various cell nodes is a major determinant of the overall speed of the program/erase scheme. One factor having a very large effect on the recovery time of a particular program/erase scheme is the parasitic capacitance that is formed between the various nodes of the floating gate cell. These capacitances are illustrated in FIGS. 1 and 2 as C1 (the gate to PWI capacitor), C2 (the PWI to NWD junction capacitor), and C3 (the NWD to P-substrate junction capacitor). Thus far, three conventional schemes have been used to discharge C1, C2, C3, and recover all the terminals of the cell to ground.
The first scheme is illustrated in FIGS. 3(a)-(c) with respect to a recovery from a program step. This scheme consists of first connecting the cell's gate to ground via a highly conductive path, thereby coupling node PWI to a lower potential by capacitor C1 (-17 volts in this case) since PWI is connected to -9 V by a low conductive path. Thus, in order to reduce this coupling, this scheme is typically modified by connecting the gate to ground by a low conductive path and consequently prolonging the recovery time. Further, as shown in FIG. 3(b), a voltage limiter D3 is also typically provided in order to provide the node with protection from a high voltage stress caused by a miscalculated coupling. After the gate terminal is discharged to ground, PWI is discharged to ground via another path. At this moment, the same coupling problem appears again. As illustrated in FIG. 3(c), the gate will be coupled to a positive potential by C1 if the gate-to-ground path is not highly conductive enough to maintain the gate at ground, and NWD is thus coupled to +12 volts via C2. Therefore, this particular recovery scheme requires a negative potential limiter D3, and two separate drivers to connect the gate to ground at different time intervals. A weak gate driver is needed for the first step to ensure that PWI is not coupled too low, and a strong gate driver is needed to ensure that the gate is not coupled high when PWI is discharged to ground.
The second scheme is illustrated in FIGS. 4(a)-(c) with respect to a recovery from a program step. This scheme is just the reverse of the above scheme, it discharges PWI first, then the gate. A positive potential limiter D5 must therefore be connected to the gate terminal to avoid a strong coupling high via C1 during the first step if a strong driver is used to connect PWI to ground. Similarly, PWI must be connected to ground via a highly conductive path while the gate is discharged to ground to avoid PWI being coupled to -12 volts.
Another scheme that has been utilized is illustrated in FIGS. 5(a)-(b) with respect to a recovery from a program function. In this scheme, both PWI and the gate are discharged to ground at the same time. To implement this, the driving ability to the ground at the gate terminal must be roughly equal to the ground driving ability at PWI to balance the coupling by C1. Otherwise, the clamp circuits D3 and D5 used in the aforementioned schemes are needed to limit voltage swings at the terminals. If equal driving is adapted without the use of a clamp circuit, the precise capacitance estimation of C1, C2, and C3 is crucial to the proper operation of a circuit implementing this scheme. In addition, as C2 and C3 are junction capacitors whose capacitance varies with the potential difference between the two terminals of the capacitors, then C2 and C3 become voltage dependent variables during the recovery period. This variation greatly complicates the precise estimation of C1, C2, and C3 that is needed to implement this scheme.
FIGS. 3, 4, and 5 were discussed above with respect to recovery from a program function. Each of the above three recovery schemes could be applied to a recovery from an erase function as well--only the polarities of the voltages would change. Similarly, the problems discussed above with respect to the program function recovery apply equally with respect to an erase function recovery.
In summary, it has been found that currently utilized schemes to recover the terminals of a triple well floating gate cell after a program or erase function are somewhat limited. In particular, these schemes are limited in the speed at which they can perform the recovery function. This speed limitation is caused by the problems inherent in parasitic coupling between the various nodes of a triple well floating gate cell that has been programmed/erased. Accordingly, it is desirable to provide a scheme to recover a triple well floating gate cell from a program and/or erase function which overcomes the problems of the prior art as set forth above. Further, it is desirable to provide a circuit which will implement such a scheme, and that is capable of being implemented on an integrated circuit with a flash memory cell.